Telecommunication modules, implemented in programable devices
Telecommunication applications requiring high processing speed (for example: high speed digital transmission), can be implemented in programmable logic devices.
Our company has developed number of modules for complex telecommunication devices (framers, protocol controllers, fuly digital phase loops) designed for implementation in ALTERA FPGA programmable logic devices.
Complete E1 (2048kbit/s) line transiver, includes G.704 framer, G703 codec and clock recovery module.
HDLC protocol controller
HDLC protocol controller (HDLC - high-level data link controller),
used for error-free packet ransmission between network nodes.
Digital phase loop
Fully digital phase loop, with programmable DDS device (Direct Digital Syntehzis), acting as VCO generator.
ATM cells transceiver for plesiochronous G.804 line.
Allows inserting and cell mapping of ATM cells in G.704 framed 2048 kbit/s stream, implementing ITU G.804 standard.
Optionally support of IMA controller.
ATM transceiver (I.432.1)
Allows inserting and cell mapping of ATM cells in binary stream, implementing ITU I.432.1 standard.
Plesiochronous 4xE1 (G.742) multiplex/demultiplex
Implementation of plesiochronous multiplex/demultiplex of four E1 (2048 kbit/s) streams into one E2 (8448 kbit/s) stream.
Transreceiver of STANAG 4206 and EUROCOM D/1 families digital lines
Set of functions, implementing transmitter and receiver, compatible with STANAG 4206 and EUROCOM D/1 families. Includes line code codec (biphase-differental or AMI), framer, and signalization channel transceiver with error correction.